The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to forming gate structures in integrated circuit devices.
As integrated circuit (IC) technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings.
Stressing gate regions in IC devices is an effective mechanism for improving the performance (e.g., speed) of signals passing through those gate regions. However, as device dimensions are reduced, the distance (pitch) between adjacent IC gates is reduced. This reduced gate pitch makes it more difficult to effectively stress the gate region during formation of the IC, negatively affecting performance. Further, reduced gate pitch can lead to reduced contact resistivity, contact-to-gate shorts, as well as other undesirable conditions.